An Efficient Retargetable Simulator SIM-A for ASIP DSE and Validation with RISC and VLIW based Processors

Abstract

General Purpose Processor (GPP) provides high application flexibility but at a high cost in terms of more silicon area, high power consumption and low performance. In systems where high application flexibility is not required, it is possible to trade off flexibility for lower cost by tailoring the processor to the application to create an Application Specific Instruction set Processor (ASIP) with high performance yet low silicon cost. If we look at the rapid rate at which mobile technology is developing and the constant need for miniaturization, ASIPs seem to be poised in a stronger position compared to ASICs. SIM-A Simulator has been developed that generates the performance estimates for the application under consideration. Processor description is captured in the form of GUI, which allows the user to specify the architecture in visual form. The cycle accurate, structural simulator generated using SIM-A allows the user to collect statistics called cycle count. The SIM-A environment has been designed to allow modeling of diverse range of processors. This has been demonstrated to an extent through the modeling of RISC processor and VLIW Processor with traditional memory hierarchies. The technique has been validated against standard toolsets.

Keywords: ASIP; Retargetable Simulator; Simulator; RISC based Simulator; VLIW based Simulator;