A SINGLE BIT ERROR DETECTION AND CORRECTION BASED ON THEMRC AND THE MP TECHNIQUES IN RRNS ARCHITECTURE

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Yaw Afriyie
M.I. Daabo

Abstract

This paper presents some results on single error detection and correction based on the Redundant Residue Number System (RRNS).The proposed technique utilizes the Mixed Radix Conversion (MRC) and the Modulus Projection (MP) algorithms that significantly simplifies the error correction process for integers. The MP considerably reduces the computational steps and hardware architecture and further improve the processing speed. This results in a considerable improvement in the speed by  and tends to require about  less hardware resources in the proposed scheme when compared with the existing scheme used in this work. The proposed scheme is built on simple adders in the design of the architecture which saw a considerable improvement in both area and speed in as compared to the work by Yangyanget. al [6] which used ROMs and latches for the design of their architecture.

 

 

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References

H. L. Garner, (1959), “The residue number system,†IRE Trans. Electronic Computers, Vol. 8, pp. 140-147.

F. Barsi& P. Maestrini, (1973), “Error Correcting Properties of Redundant Residue Number Systems.IEEE Transactions of Computers, Vol. 22, No. 3, pp. 307–315.

A.F Behrouz, (2008). Data Communications and Networking. Fourth Edition. Error Detection and Correction Computer, Vol. 23, No. 7, pp. 267-306.

D. M. Mandelbaum, (1972), “Error correction in residue arithmetic,†IEEE Trans. Comput., Vol. 21, No. 6, pp. 538-545.

Szabo, N. & Tanaka, R. (1967). Residue Arithmetic and its Application to Computer Technology. MC-Graw-Hill, New York.

Yangyang T., Boutillon E., Jégo C., &Jézéquel M.(2008). A new single-error correction scheme based on Self-Diagnosis Residue Number Arithmetic. Conference on Design and Architectures for Signal and Image Processing (DASIP) pp. 27–33. doi: 10.1109/DASIP.2010.5706242

W. K. Jenkins, C. Radhakrishnan, & S. Pal (2007), Fault Tolerant Signal Processing for Masking Transient Errors in VLSI Signal Processors,†Proceedings IEEE International Symposium on Circuits and System (ISCAS), pp. 2570 – 2573

O. Goldreich, D. Ron & M. Sudan (2000). Chinese Remaindering with Errorsâ€, IEEE Trans. Infor. Theory, Vol. 46, pp.1330-1338.

M.I. Daabo,&K.A. Gbolagade(2014). An Overflow Detection Scheme with a Reverse Converter for the Moduli set {2^n-1,2^n,2^n+1}. Journal of Emerging Trends in Computing and Information Sciences, ISSN 2079-8407, Vol. 5, No. 12, pp. 931-935.

A.S. Molahosseini, &K. Navi(2007). New Arithmetic residue to binary Converters.

International Journal of Computer Sciences and Engineering Systems, Vol. 1, No.4, pp. 295-299.