Design Analysis of AND (2T) and OR (2T) Based Low Power Full Adder Circuit

Abstract

With the increase in demand for circuits with lower power dissipation, we put forward the following Full Adder circuit. New method is proposed to implement the Full Adder functions. The main design objective for this Full Adder circuit is low power dissipation. The AND and OR gates in the Full Adder circuit (CMOS logic) are replaced by 2T AND and 2T OR gates. The proposed designs are compared with previously known circuits and they show to provide superior performance. The proposed circuit is verified using Tanner EDA v15.0 Tool.

Keywords: AND gates, OR gates, XOR gates, Full Adder