Recovery of TSV Based 3D IC
Main Article Content
Abstract
Downloads
Article Details
COPYRIGHT
Submission of a manuscript implies: that the work described has not been published before, that it is not under consideration for publication elsewhere; that if and when the manuscript is accepted for publication, the authors agree to automatic transfer of the copyright to the publisher.
Authors who publish with this journal agree to the following terms:
- Authors retain copyright and grant the journal right of first publication with the work simultaneously licensed under a Creative Commons Attribution License that allows others to share the work with an acknowledgment of the work's authorship and initial publication in this journal.
- Authors are able to enter into separate, additional contractual arrangements for the non-exclusive distribution of the journal's published version of the work (e.g., post it to an institutional repository or publish it in a book), with an acknowledgment of its initial publication in this journal.
- Authors are permitted and encouraged to post their work online (e.g., in institutional repositories or on their website) prior to and during the submission process, as it can lead to productive exchanges, as well as earlier and greater citation of published work
- The journal allows the author(s) to retain publishing rights without restrictions.
- The journal allows the author(s) to hold the copyright without restrictions.
References
. R. Weerasekera et al, “Extending Systems-on chip to the Third Dimension: Performance,Cost and Technological Tradeoffs,†in Int. Conference on Computer-Aided design, pp.212-219, 2007.
. H. Chen, J.-Y. Shih, S.-W. Li, H.-C. Lin, M.-J. Wang, and C.-N.Peng., “Electrical tests for three-dimensional ics (3dics) with tsvs,†in Proc. of 3D Test Workshop Informal Digest, 2010.
. Yi Zhao, Saqib Khursheed, Bashir M. Al-Hashimi, “Cost-Effective TSV Grouping for Yield mprovement of 3D-ICsâ€, in Proc. Asian Test Symposium, pp: 201-206, 2011.
. Ang-Chih Hsieh, TingTing Hwang, Ming-Tung Chang, Chih-Mou Tseng and Hung-Chun Li, “TSV Redundancy: Architecture and Design Issues in 3D ICâ€, in Proc. DATE, pp: 166-171, 2010.
. Surajit Kumar Roy, Sobitri Chatterjee, Chandan Giri and Hafizur Rahaman,“Repairing of Faulty TSVs using Available Number of Multiplexers in 3D ICsâ€, in Proc. Of ASQED, pp 155-160, 2013.
. U. Kang, et al. 8 Gb 3-D DDR3 DRAM using through-silicon-via technology. IEEE Journal of Solid-State Circuits, 45(1):111–119, Jan.2010.A.C.
. Hsieh, et al. TSV redundancy: Architecture and design issues in 3D IC. In Proc. Design, Automation, and Test in Europe Conf. Exhibition,pp. 166–171, 2010.
. Li Jiang, Qiang Xu, and Bill Eklow : On Effective TSV Repair for 3D-Stacked ICs. Design and Automated test in Europe ,2012.
. I. Loi, et al. A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. In Proc. Int’l Conf. on Computer-Aided Design,pp. 598–602, 2008.
. Surajit Kumar Roy, Kaustav Roy, Chandan Giri and Hafizur Rahaman : Recovery of Faulty TSVs in 3D ICs, 16th Int'l Symposium on Quality Electronic Design, pp 533-536,2015.F.
. Ye and Krishnendu Chakrabarty “TSV Open Defects in 3D Integrated Circuits: Characterization, Test and OptimalSpare Allcationâ€, in Proc. DAC, pp: 1024-1030,2012.
. Jing Xie, Yu Wang and Yuan Xie, “Yield-Aware Time-Efficient Testing and Self-fixing Design For TSV-Based 3D ICs†in Proc.Asia and South Pacific Design Automation Conference (ASPDAC),pp: 738 - 743, 2012.
. M. Kawano, et al. A 3D packaging technology for 4 Gbit stacked DRAM with 3 Gbps data transfer. In IEEE Int’l Electron Devices Meeting, pp.1–4, 2006.
. T. Zhang, et al. A customized design of DRAM controller for on-chip 3D DRAM stacking. In Proc. IEEE Conf. on Custom Integrated Circuits, pp. 1–4.