Comparative Study and Analysis of Universal Gates for Minimizing Power and Delay using Lector Technique
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Abstract
The main objective of this paper is to provide new low power solutions for Very Large Scale Integration (VLSI) designers The power consumption of the electronic devices can be reduced by adopting different design styles. Lector logic style is said to be an attractive solution for such low power electronic applications. The proposed technique has less power dissipation when compared to the conventional CMOS design style. Various techniques at the different levels of the design process have been implemented to reduce the power dissipation at the circuit, architectural and system level. In this paper, Conventional NAND gate and Nor gate are designed and then compared with the Lector NAND and NOR using 180nm technology.
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Keywords: Power dissipation, delay, transistors, leakage power, Lector, CMOS.
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