Reduced Hardware Cordic Based 16 Point Fft Processor
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Abstract
This project presents a 16 point FFT processor based on a Reduced Hardware CORDIC Algorithm. The proposed algorithm utilizes a new rotation scheme which uses only two angles as the rotation angles. In this proposed scheme, we do not want to store the twiddle angles. Thus there is reduction in the number of hardwares required, which results in a considerable reduction in the power and total memory used. Then the performance of 16 point FFT processor based on proposed reduced hardware CORDIC algorithm is compared with 16 point FFT processor based on conventional CORDIC algorithm. The synthesis results match the theoretical analysis and it can be observed that more than 50% reduction can be achieved in total memory used. In addition, the dynamic power consumption can be reduced by as much as 30% by reducing memory accesses.
Keywords: Cooley- Tukey, CORDIC, FFT, low power, VLSI
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