Shuffle-RAT: An FPGA-based Iterative Block Cipher

Rajdeep Chakraborty, Sananda Mitra, J. K. Mandal


Proposed FPGA based technique considers a message as a binary string on which Shuffle-RAT is applied. A block of n-bits is taken as
an input stream, where n ranges from 8 to 256 – bit, then Shuffle-RAT is applied in each block to generate intermediate stream, any one
intermediate stream is considered as a cipher text. The same operation is performed repeatedly on various block sizes. It is a kind of block cipher
and symmetric in nature hence decoding is done in similar manner. This paper also presents an efficient hardware realization of the proposed
technique using state-of-the-art Field Programmable Gate Array (FPGA). The technique is also coded in C programming language and Very
High Speed Integrated Circuit Hardware Description Language (VHDL). Various results and comparisons have been performed against
industrially accepted RSA and TDES. A satisfactory results and comparisons are found.


Keywords: cryptography; iterative block cipher; modulo-addition; RAT; FPGA.

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