An efficient HW/SW implementation for Wavelet-based t+2D Video Coding

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Mehrez Marzougui
Jamel Baili, Mohamed Atri

Abstract

In recent years, video compression has emerged as an effective technique to reduce spatial and temporal redundancy in video sequence. Temporal redundancy reduction deals with motion estimation and motion compensation algorithm with the matching technique to produce the next encoded video frame with motion vector. However, computational complexity and resource sharing of the motion estimation algorithm poses great challenges for real time applications. Dealing with these issues, the first part of this paper focuses on a system-level implementation of a wavelet-based t+2D video coding. Three blocks matching algorithms are implemented in order to evaluate the overall system performance. In fact, since the chip design and layout process is time consuming and expensive, it is very important to be able to predict the overall system performance in a high-level implementation before its circuit layout is deployed. The aim is to discuss the impact of different block matching motion estimation algorithms on video coding performance. Because of the complexity of the entire motion estimation system, decision in choosing one algorithm versus the other algorithms is often empirical and crucial. The paper presents also an efficient HW/SW codesign architecture for the proposed video encoder and its FPGA implementation. Each module of the encoder is investigated to find which approach between HW and SW is better to achieve overall performances such as real-time processing speed and flexibility.

Keywords: motion estimation, block matching algorithm, t+2D wavelet transform, video compression, HW/SW codesign, MPSoC.

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