A Modified Low Power FFT/IFFT Processor for OFDM Applications

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S. Lavanya
Ms.M. Jasmin

Abstract

Orthogonal Frequency Division Multiplexing (OFDM) often require an inverse fast Fourier transform (IFFT) to produce multiple subcarriers.
The read-only memories (ROM’s) used to store the twiddle factors, are eliminated in the proposed architecture which applies a
reconfigurable complex multiplier and bit-parallel multipliers to achieve a ROM-less FFT/IFFT processor .It adopts a single-path delay feedback
style as the proposed hardware architecture, thus consuming lower power than the existing methodology.


Keyword: single-path delay feedback, bit-parallel multipliers, low power.

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