An FPGA Implementation of an Adaptive Algorithm for Data Reduction in Wireless Sensor Network

Sayed Azizuddin, Prof. P. H. Rangaree


Power saving is a major concern in wireless sensor network and researcher, engineers are working hard to solve energy related problem in wireless sensor network. The wireless sensor network is wireless network with each node consist of a wireless node i.e. wireless transreceiver and a sensor witch picks up the information such as temperature, light, humidity, voltage, radiation etc and send it to sink node. Sink node receive the information from the source node which is connected to the sensor and forward it to the main data processing machine which ultimately utilized the sensed information. Here we proposed that the Data transmission between Source node and sink node can be reduced if we deploy a predictive filter at the both end i.e. transmitter side and a receiver side so the data reported to sink node will be reduced drastically and hence power can be saved and battery operated node transmitter can work for longer duration. Here FPGA design for predictive filter is shown the code are written in VHDL using Xilinx ISE tool.


Index Terms : Adaptive filters, Digital signal processing, FPGA, LMS filter, Simulink model, Wireless sensor Network, Xilinx ISE tool.

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