An Efficient Algorithm for Tile Size Selection
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Abstract
Loop tiling is a well-known compiler transformation that increases data locality exposes parallelism and reduces synchronization costs. Tiling increases the amount of data reuse that can be exploited by reordering the loop iterations so that accesses to the same data are closer together in time [2]. Loop tiling is effective to improve hit ratio of cache. However, while eliminating self interference miss, tiling may produce small tiling factors for the cases of some arrays [3]. This paper presents a new algorithm for choosing problem-size dependent tiles based on the cache size, cache line size that eliminates the self-interference misses and uses 100% of available cache size. This algorithm covers the entire problem array size with the selected tile size. The tile size selection is our choice, so based on the different tile sizes available for A[i][j], we can choose a rectangular or square tile size.
Keywords: Loop tiling, self interference miss, and cache line size.
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