A SINGLE BIT ERROR DETECTION AND CORRECTION BASED ON THEMRC AND THE MP TECHNIQUES IN RRNS ARCHITECTURE

: This paper presents some results on single error detection and correction based on the Redundant Residue Number System (RRNS).The proposed technique utilizes the Mixed Radix Conversion (MRC) and the Modulus Projection (MP) algorithms that significantly simplifies the error correction process for integers. The MP considerably reduces the computational steps and hardware architecture and further improve the processing speed. This results in a considerable improvement in the speed by 𝟗𝟕% and tends to require about 𝟗𝟔% less hardware resources in the proposed scheme when compared with the existing scheme used in this work. The proposed scheme is built on simple adders in the design of the architecture which saw a considerable improvement in both area and speed in as compared to the work by Yangyang et. al [6] which used ROMs and latches for the design of their architecture.


INTRODUCTION
The increasing demand for speed and accuracy in digital communication has led to the introduction of parallel computing. RNS is a form of parallel computing that was first introduced by Garner [1]. RNS provides a very fast arithmetic due to its capability of performing the carry-free operations, i.e. addition, subtraction and multiplication. RNS also possesses parallel and fault tolerant features, which are seen to be helpful for hardware implementation. Barsi and Maestrini [2] in their work posited that RNS offers a great speed as a result of its carry-free nature. Because of this, these have led to the increase in the development of a number of error detection and error correction algorithms based on RNS. When some redundant residues are added, the RNS has the possibility of error detection and correction, hence, the term Redundant Residue Number System (RRNS). Redundancy is achieved through various schemes in RNS. Behrouz [3] indicated that the ratio of the redundant bits to information bit is important to any scheme. There are significant works by Mandelbaum [4] and Szabo [5] concerning RRNS in the detection and correction of errors. Some concepts such as legitimate and illegitimate range for consistency checking related to error techniques are also studied. An algorithm that is based on the detection and correction of single bit errors by Szabo and Tanaka [4] allowed for scaling by a product moduli from the RNS based on clock cycles. The main difficulty in their work was that the scaling reduced the processing speed. The clock cycles denotes the time required for the elementary operation. In the work by Yangyang et. al [6], a discussion of a single bit error correction algorithm that implements ROMs and latches were used. The cost of ROMs and latches are however expensive to build affecting both the area and delay of the architecture. Some useful investigations were conducted by Jenkins et. al [7] to detect and correct single bit errors based on the Mixed Radix Conversion (MRC) and the Base Extension (BEX) techniques to RRNS application in digital filters and residue number error checkers due to efficient pipeline architectures. Goldreichet. al. [8], proposed a performance evaluation of Residue number based on the Chinese Remainder Theorem (CRT) in the detection and correction of errors in RRNS. The resulting effects of the schemes in [5]- [8] when compared to the MRC and the MP proposed in this work offer a low complexity and detects and corrects single bit errors faster. To this effect, the proposed scheme offers a great advantage in terms of area cost, delay and would be able to detect and correct single bit errors faster. In this paper, we propose a new scheme that will show the effectiveness of the RRNS based on MRC and the MP that will detect and correct bit single errors.

II. RESIDUE ARITHMETIC FUNDAMENTALS
RNS is characterized by a set of k pairwise relatively prime positive integers, i.e. the greatest common divisor gcd( , ) =1 with ≠ , 1 , 2 … −1 , called the moduli, that is formed in increasing, i.e., 1 < 2 < ⋯ < −1 < [3]. Their products represent the interval [0, M) called the legitimate range that defines the useful computational range of the number system, that is, To represent positive and negative numbers, the dynamic range is defined as −( − 1 2 , (( − 1) 2 if is odd and /2 if is even. Every natural integer in the legitimate range can be represented by a set of residues 1 , 2 …, −1 , where With i ϵ [1, k] and |X | denotes X modulo . Due to the carryfree property, the three operations namely addition, subtraction and multiplication can be operated with respect to the moduli independently, i.e. 1 , 2 … * * 1 , 2 … = 1 , 2 … , ≡| * | (3) With * denotes the three operations. Consequently, RNS is able to provide a fast arithmetic.

III.
CONVERSION It is well known that MRC and CRT are approaches that are often applied in conversion. This can be seen in the work of Mandelbaum [4]. This study will be limited to the MRC and the MP techniques because the real time implementation of the CRT involves a modular operation with a large integer which results in large complexities. Daabo [9] indicated that to prevent the computations with such larger M, the CRT satisfies the real-time signal processing time due to its parallel means of computation and there is a constant limit to this approach. The process of converting from conventional representations to RNS is known as forward conversion whilst converting from the RNS to the conventional representations is known as the reverse conversion. The residue to conventional number representation is done mainly by the MRC or the CRT as seen in the work of Mohahosseini [10]. The MRC is carried out by a weighted approach. The MRC is expressed by the following equations; X = 1 + 2 1 + 3 1 2 + 1 2 3 … −1 (4) where , =1, is the Mixed Radix Digits (MRDs) can be computed as: This paper presents an efficient algorithm for detection and correction of single bit errors for the moduli set 2 n − 1, 2 n , 2 n + 1, 22n−3, 22n+1+1. The rest of this paper is organized as follows: Section 4 presents the proposed method. In Section 5, the hardware implementation of the proposed scheme is presented, a simplified algorithm with numerical illustrations are also presented. The performance of the proposed scheme is evaluated in Section 6 whiles the paper is concluded in Section 7.

IV. PROPOSED METHOD
This section provides a new method for detecting and correcting single bit errors in RRNS in the given moduli set.

VI. Proposed Architecture
The residue number is converted to the Mixed Radix System (MRS) in parallel with the computation of the MRS, which detects and corrects primarily based on the non-redundant part. In the event of an error in any of the channels, the redundant part will be employed in the detection and correction of the residue digit error.The Mixed Radix Digits (MRDs) are computed according to equation (24) where all the MRDs 1 , 2 and 3 are computed individually in equations (21) to (23). The which are the MRDs for the non-redundant part are computed separately which is seen in Figure 1. As shown in Figure 1, 3 is computed using Carry Save Adders (CSAs) 1, 2 and 3 and two regular ( + 1) bit Carry Propagate Adders (CPAs) 1 and 2 respectively. All the CSAs require an area of ( + 1)∆ each whilst CPAs 1, 2 and 3 require an area of each. In order to obtain the MRD 3 will require a total area of (11 + 4)∆ . Regarding the delay, CSA (i.e. CSAs 1, 2 and 3) impose a delay of each in the reverse convertor. CPAs 1 in the reverse convertor require a delay of (4 + 2) . CPAs 2 and 3 in the reverse convertor require a delay of 6 + 2 each. The reverse convertor for the MRC also has one CSA that also impose a delay on the system. The total delay needed for the proposed scheme is (10 + 7) . The schematic diagram for the proposed scheme is shown in Figure 1. The schematic diagrams for the proposed scheme are shown below.

VII. Numerical Results
Let us now consider some numerical illustrations with the proposed scheme. Consider an ( , ) code where n is the length of the code and k is the dimension of the code with the moduli set 1, 2 , 3 , 4 , 5 = (3,4,5,13,17) where 1 , 2 and 3 are non-redundant moduli, 4, 5 are the redundant moduli. We consider the integer message X=57, for its residue digits are = (0, 1, 2, 5, 6). The legitimate range = = 3*4*5=60 and the illegitimate range = = 13*17 =221. Assume that during storage or computation, an error occurs in the second residue digit such that 2 =3. Therefore, the received codevector will be = (0, 3 , 2, 5, 6). (3 + 1) CPA 3 6687 13 = 6687 1020 = 567 6687 17 = 6687 780 = 447 From the above calculation, it can be observed that there is only one legitimate projection with respect to the second moduli 2 = 4 which falls within the legitimate range and it is the word most likely sent. It can be seen and concluded from the above projections that the second residue ( 2 ) is in error and hence, anytime it is involved in computation an erroneous output will be executed. Using the same illustration given above, we now consider detecting and correcting the error using the moduli set. The result for the iterative processes are shown below; 1 , 2 , 3 , 4 = 1234 = 447 1 , 2 , 3 , 5 = 1235 = 747 1 , 2 , 4 , 5 = 1245 = 1383 1 , 3 , 4 , 5 = 1345 = 57* 2 , 3 , 4 , 5 = 1345 = 2272 From these results, it could be observed that whenever 2 is involved in the computation it gives an illegitimate value i.e. 1234 , 1235 , 1245 and 1345 . When 2 was discarded in the 1345 , the recovered data is 57 which clearly indicates that 2 is the erroneous digit. The conclusion is that the correct result is 57 and the error, which occurred in, 2 can be corrected by computing 2 = 57 4 = 1.

VIII. PERFORMANCE EVALUATION
The ability to detect and correct errors in a digital system improves its reliability and integrity. In this work, the MRC decoding technique is compared with the MP. It is found that the MRC decoding processes result in more computational steps in detecting and correcting errors in RRNS by dropping a residue at a time. The MP on the other hand detects and corrects single bit errors without going through more iterative steps in its implementation. A theoretical analysis shows that the MP recovers integer messages faster and improves computational speed than the MRC decoding processes as shown in Figure 2.
To evaluate the performance of the proposed scheme, the work is compared with Yangyang et. al [6]. Theoretically, the proposed scheme has less delay and computational complexity without compromising on accuracy as shown in Figures 3 and 4. Also, the proposed design employs simple adders (CSAs and CPAs) for its implementation. In the scheme of Yangyang et. al [6], twenty (20) latches which has an area of 9 and nine (9) ROMs with an area of 4 2 were employed and that resulted into a total area requirement of (40 2 + 20 )∆ .

IX. CONCLUSION
The need to have efficient and faster algorithm in detecting and correcting errors cannot be ignored in digital systems. The algorithm presented is premised on both the Modulus Projection and the Mixed Radix Conversion. The MP considerably reduced the iterative steps and improved the speed of the architecture. Generally, the proposed scheme was built using simple adders instead of ROMs and latches that are associated with high cost of implementation. An area/delay analyses showed that there is a considerable improvement in the speed by 97% and tends to require about 96% less hardware resources in the proposed technique.