FAULT TOLERANCE OF ADVANCED IRREGULAR SHUFFLE EXCHANGE NETWORK (AISEN)

Multistage interconnection networks (MINs) are class of high-speed, most efficient interconnection networks (INs) which are used for multiprocessor systems. In present research, fault tolerance is a critical issue. We have proposed a new fault tolerant irregular MIN named as Advanced Irregular Shuffle Exchange Networks (AISEN) and compared it with existing Irregular Augmented Shuffle Exchange Network-2 (IASEN-2) and Modified Alpha Network (MALN). It has better fault tolerance capability as compared to existing IASEN-2 and MALN in terms of non-faulty and faulty conditions.


INTRODUCTION
Multistage Interconnection Networks (MINs) is a high performance interconnection network, which plays a vital role in parallel processing systems and broadband switching technology. Multistage Interconnection Network (MIN) is formed by many stages of interconnected switches and has low cost and high reliability. Fault tolerance is a critical issue of MIN [7] [9]. A number of regular and irregular networks have been proposed for increasing the ability of fault tolerance in MINs. We propose an Advanced Irregular Shuffle Exchange Network (AISEN) and its routing algorithm, which provide enhanced fault tolerance capacity as compared to MALN and IASEN-2 in terms of different parameters like throughput, processor utilization, processing power, bandwidth etc. AISEN is a single fault tolerant network, it means that network can tolerate fault when a single switch is faulty in every stage. So, AISEN is compared with MALN [3] and IASEN-2 [5] for faulty (single fault) and non-faulty situations.
In this paper, section I presents introduction, section II describes structure of the existing networks, section III describes structure and design of proposed network AISEN. Section IV describes performance evaluation parameter, section V presents Comparison, and Analysis is of proposed network AISEN and existing IASEN-2. At last, conclusion and future work are given in section VI.

II. STRUCTURE OF EXISTING NETWORKS
In MINs, fault tolerance provides alternate path in case of a fault in a link or switch. The proposed network handles switch failure problems and increased performance. Several research works have been done for increasing the fault tolerance of MIN and various networks also have been proposed. This section discuss the basic structure of existing fault tolerant network modified alpha network (MALN) [3] and irregular augmented shuffle exchange networks-2 (IASEN-2) [5].

A. Irregular Augmented Shuffle Exchange Networks-2
(IASEN-2) IASEN-2 [5], is modified form of IASEN [10] MIN, consists of N number of source address and destination address with n=log 2 N stages. Each source address is associated with multiplexer (M) of size 2x1and each destination address associated with demultiplexer (DM) of size 1x2. Each first and last stage is associated with N/2 switching elements (SE). The first stage and last stage have SEs of size 2x3 and 3x2 respectively but SE of second and third stage has size 9x3 and 3x9 respectively. The SEs of each stage is associated with each other through alternative links.

B. Modified Alfa Networks (MALN)
Modified Alfa Networks (MALN) [3] consists of NxN network size with (2m-2) stages where m=log 2 (N/2). All sources and destinations are linked with the multiplexers of size 2x1 and demultiplexers of size 1x2 respectively. All stages except last stage consist of 2 n no. of switching elements (SE) of size 3x3 and the last stage consists of 2 n-1 no. of switching elements of size 2x2. The network is divided into two identical sub-networks G0 and G1. If a SE is faulty in any stage then message will be route through auxiliary or alternate link.  In AISEN, SEs of one stage connected with the SEs of next stage as shown in Fig 2. Each source or destination is connected with three SEs of its stage through multiplexer or demultiplexer respectively. For example, source 0 is connected with SE 'a' and SE 'c'. Therefore, we can say that SE 'a' is the Primary SE and SE 'c' first alternate SE. Similarly in second stage, SE 'i', 'j' are primary and first alternate SEs respectively for 'a', 'b', 'c' and 'd' while SE 'j' and 'k' are primary and first alternate for 'e', 'f', 'g', and 'h'. In third stage, SE 'n' and 'l' are primary and first alternate SEs respectively for destination 5. Similarly, we can find primary and first alternate SE for other sources and destinations. Therefore, at least one of the required SE i.e. primary or first alternate SEs of each stage should be in working condition for data transmission from given source to its destinations otherwise network will be failed and data transmission will be stopped.

A. Routing of Proposed Network
In AISEN routing algorithm, the source address, and its corresponding destination address are given. Then data packet is transferred from given source address to its primary switching element (PSE 1 ) of first stage. If PSE 1 is faulty or busy then data packet will be transferred to its alternate switching element (ASE 1 ) of first stage. If both of these SEs i.e. PSE 1 and ASE 1 are faulty then it will be considered that network is fail and request will be dropped otherwise send data packet to the primary switching element (PSE 2 ) of next stage. If primary switching element (PSE 2 ) of second stage is faulty or busy then data packet will be transferred to alternate switching element (ASE 2 ) of second stage. If these two i.e. PSE 2 and ASE 2 are faulty then network will be considered as fail and request will be dropped otherwise send data packet to primary switching element (PSE 3 ) of third stage. If PSE 3 is faulty or busy then send data packet to its alternate switching element (ASE 3 ) stage third. If both of these SEs i.e. PSE 3 and ASE 3 are faulty then network will be considered as fail and request will be dropped otherwise data packet will be transferred to its given destination address.

IV. PERFORMANCE EVALUATION PARAMETERS
Between each source-destination pair, the data packet takes the minimum path in data transmission process when the network is non-faulty (or no fault in switches). The data packet is rerouted from faulty node to non-faulty node if a single switch fault occurs in network. Thus, the routing time of data packets between two nodes will be double in faulty case as compared to non-faulty case. For example, let the routing time of data packets between two non-faulty nodes is 0.01 ms and for single switch fault is 0.02 ms [6].

A. Request Generation Probability (p)
The number of data or information packets delivered on a source node and these packets can be conveyed to N destinations over MINs is known as Request Generation Probability (p) or Load Factor [1] [2]. The value of p is assumed to be 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, and 1.

B. Data Transmission Time
It is time that all generated data packets take from source to the given number of destinations [8].
If network is non-faulty, then it is given as follows: T = (N n -1) x T n x N dp x D n If network has single switch fault, then it is given as follows: T SF = T D + (S t x T) Where, N n =Number of nodes including source and destination T n = Routing Time between two nodes D n =Number of destinations N dp = Total number of generated data packets on a source node S t = total number of stages T= If network is non-faulty, then data transmission time T SF = If network is single switch faulty, then data transmission time.

C. Bandwidth
"The average number of dynamic memory modules per unit time is known as bandwidth" [1][2] [3]. For S n sources and D n destinations, the bandwidth is calculated as follows: BW= D n x p n

D. Probability of Acceptance (PA)
"PA is the number of request acknowledged by the destination side, which is sent by the source side in a transmission cycle" [1][2] [4]. It is calculated as follows:

E. Throughput
"The average number of data or information packets transferred successfully from a source to destination pair in a MIN is known as throughput" [1][2] [4].
In other words, the maximum number of traffic acknowledged by a MIN per unit time is called throughput.

F. Processor Utilization (PU)
"PU is the percentage of time the processor is dynamic doing calculation without getting to the global memory" [1][2] [4].

G. Processing Power (PP)
Processing power can be determined on behalf of processor. The aggregate of processor utilization over the number of processors is called processing power. It is given as follows: PP= (N×PU)

V. COMPARISON AND ANALYSIS
In this section, the performance analysis is calculated with the help of performance evaluation parameters for IASEN-2 [5], MALN [3] and AISEN and their comparison is also performed in faulty (or single switch fault) non-faulty conditions. Let the data packets are transferred from source 1 to destination 4. We assume that the routing time between two nodes is 0.01 ms in non-faulty condition and 0.02 ms for faulty (or single switch fault) condition. The node can be anything such as source, destination, or SE. Let the value of request generation probability or offered load (p) is 0.1, 0.

C. Throughput (TP)
Performance comparison of throughput is given in Fig. 6 and Fig. 7. in non-faulty (without fault) and faulty (single switch fault) conditions respectively.

D. Processor Utilization (PU)
Processor utilization of AISEN is better than IASEN-2 and MALN in both conditions.

VI. CONCLUSION
In this paper, the proposed fault tolerant MIN performs better than the IASEN-2 and MALN. The routing algorithm and performance analysis shows that AISEN is a single switch fault tolerant MIN at each stage of the network and performs data transmission efficiently. The network design of AISEN can be changed and applied on other MINs to obtain more fault tolerant network at optimum cost in future.